It is well known that the drive currents of metal-oxide-semiconductor (MOS) devices are affected by the stresses applied on their channel regions. The stresses in the channel regions may improve or degrade the carrier mobility depending on the direction of stresses. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device, and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device, e.g. for <110> channel on (100) Si substrate.
Although the beneficial stresses in the channel regions are generally desirable, it is also realized that the magnitude of the drive current improvement is related to the magnitude of the stress. Further, an incorrect stress direction, such as compressive stress in the transverse direction, may degrade the mobility and subsequently the current, which should be minimized. On a same semiconductor chip, the MOS devices may be applied with stresses having different magnitudes. Accordingly, the drive current improvements or degradations for different MOS devices may be different, resulting in non-uniform drive currents, and hence non-uniform drive current drifts.
For each of the MOS devices in a semiconductor chip, the respective spacing from other MOS devices affects its performance. The spacing may be filled with shallow trench isolation (STI) regions (or field regions). Due to the inherent stress of the insulation materials, the STI regions apply stresses to adjacent MOS devices, and the magnitudes of the stresses are affected by the spacing. The variations in the spacing cause variations in the stresses generated by STI regions. Therefore, it is difficult to predict and compensate for the drive current drifts in circuit simulations.
The performance of MOS devices needs to be predictable, so that at circuit design time, simulations may accurately reflect the circuit behavior. Accordingly, it is preferred that in a semiconductor chip at least the MOS devices of a same type circuit have a uniform performance. In the situation of non-uniform drive current drift, the drive current drift has to be compensated for during the simulations of the circuit design. What makes the compensation of the drive current drift complicated is that the stresses of MOS devices are affected by various factors and those factors behave differently for different layouts.
Conventional integrated circuit designs, however, often neglected such issues. For example, U.S. Pat. No. 5,278,105 provides a method for adding dummy regions. The method includes extracting layouts of active layers, forming blocked regions including the patterns of the active layers, and laying out dummy patterns in regions other than the blocked regions. The primary purpose of this method is to improve diffusion density for chemical-mechanical polishing (CMP) or loading effect of etching. This method places dummy diffusion patterns randomly outside the “block” layer or “keep-out region.” However, this method may have various shallow trench isolation (STI) widths even for simple rectangular diffusions as explained in the following.
FIG. 1 illustrates a conventional layout of an integrated circuit having active and dummy diffusion regions. In FIG. 1, an example layout is shown including active regions 2, 4 and 6 (active diffusion area), gate electrode strips 8, 10 and 12 (polysilicon area), and dummy regions 14 (dummy diffusion area). One skilled in the art will appreciate that the gate strips 8, 10, and 12 may be formed of materials other than polysilicon, such as metals, metal silicides, metal nitrides, polysilicon, and combinations thereof. Active region 2 and the overlying gate electrode strip 8 belong to MOS device 18, while active region 4 and the overlying gate electrode strip 10 belong to MOS device 20. It is noted that one of the dummy layer in regions 14 is spaced apart from active region 2 by spacing S1. Accordingly, the paths for applying stress (referred to as stress-application paths hereinafter) by STI regions 16 have a length S1. Similarly, one of the dummy layers in regions 14 is spaced apart from active region 4 by spacing S1. However, along another stress-application path, the stress-application path may have length S2 or S3, both different from S1. The significant difference in the lengths of the stress-application paths results in a large variation in the stresses applied by STI in region 16, and hence in a significant variation in the performance (for example, drive currents) of MOS devices 18 and 20. STI stress effect affects transistor performance parameters (such as Id-lin, Vt, Ileak, Id sat), and Id sat can be about 15˜20% off from a Spice model of the integrated circuits. For example, with a greater stress-application length S2, STI in region 16 may apply a greater stress to the channel region of MOS device 20 than the stress applied to the channel region of MOS device 18. The device drive current drift between MOS devices 18 and 20 may reach about 10 to 20 percent.
The U.S. patent application Ser. No. 12/211,503, filed Sep. 16, 2008 and entitled “Dummy Pattern Design for Reducing Device Performance Drift” describes added dummy diffusion regions for blocking stress-application paths to reduce the variations in the stresses applied to MOS devices. One described method is to add dummy diffusion stripes parallel abutting to the “block layer” and add general dummy diffusion patterns to meet a given density target. However, even though this method can make a constant STI width for simple rectangular diffusion patterns, it fails to control STI widths for non-rectangular diffusion patterns, as explained in the following.
FIG. 2 illustrates another layout of an integrated circuit having dummy diffusion stripes and general dummy diffusion patterns. In FIG. 2, an example layout is shown including block layers 202, 204, 206, and 208, where each block layer surrounds active regions 210, 212, 214, and 216 inside, and in turn dummy diffusion stripes 218 and general dummy diffusion patterns 14 surround each block layer. For the block layer 202 and 204, the spacings between the active regions (210 and 212) and dummy diffusion stripes 218 are constant, i.e. SL1 in the X direction and SW1 in the Y direction. Also for the block layer 206, the spacings between the active region 214 and dummy diffusion stripes 218 are constant for each X- and Y-direction i.e. SL2 and SW2 respectively, due to the rectangular shape of the active region 214 inside. However, for the block layer 208, there are substantial variations in the spacings between the active region 216 and dummy diffusion stripes 218 and/or general dummy diffusion patterns 14 in both X- and Y-directions, i.e. SL3, SL4 and SL5 in the X-direction, and SW3, SW4 and SW5 in the Y-direction. This is due to the irregular (non-rectangular) shape of active region 216 inside the rectangular shape of the blocked region 208. The significant difference in the lengths of the stress-application paths (spacings) results in a large variation in the stresses applied by STI in region 16, and hence in a significant variation in the performance (for example, drive currents) of MOS devices inside the block layer 208.
Accordingly, new methods for well controlled STI widths or oxide definition (OD) spacing and significantly reduced device performance variations (e.g. drive current drifts) of MOS devices regardless of diffusion shapes are needed.